EETimes
Algorithm optimization for still image decoding saves camera power and memory
By Bhavin Kharadi

EETimes
Cluster-based approach eases clock tree synthesis
By Udhaya Kumar

Electronic Design
Simulation Mismatches Can Foul Up Test-Pattern Verification
By Udhaya Kumar

EDN
FPGAs implementing high-end image-processing applications
By Pradeep Chakraborty

THREE SIXTY MAGAZINE 31, 2005
Next Frontier in Chip Design
By Rohit Dubey

SOC Central : White paper Mar 25, 2005
Elements of Verification
By Rohit Dubey

Express Computers Feb 28, 2005
4Gbps to the fore
By Venkatesh Ganesh

EE Times Feb 14, 2005
UWB gaining infrastructure
By Ron Wilson

EE Times Nov 29, 2004
Digital 'verification IP' is becoming more design-like
By Ron Wilson

EE Times Nov 08, 2004
Getting an algorithm ready for reuse
By Ketul Patel

EE Times Oct 04, 2004
Embedded test tackles verification times
By Nicolas Mokhoff

EE Times Oct 04, 2004
Inside a hybrid verification model
By Nilesh Ranpura

EE Times Oct 04, 2004
IP model shift: from blocks to app-specific subsystems
By Ron Wilson

EE Times Aug 24, 2004
Outsourcing backers say move up food chain, foes question new job claims

EE Times June 03, 2004
When requirements outrun an architecture
By Ron Wilson