ASIC-Chip Verification

ASIC / SoC / Chip Verification: With 14 years and close to 2500 man years of ASIC/SoC/Chip verification experience spanned over 145 projects across various industries, einfochips is your right choice for managed ASIC/SoC/Chip verification services & solutions to meet your product verification objectives eInfochips’ 200 engineers in ASIC/SoC/Chip division understands the importance of detecting and addressing functional errors responsible for more than 70% of Chip/ASIC/Silicon re-spins. Hence, our verification team Believes verification is an R & D project of product development/verification covering not only design/logic but architecture and software Develops a complete/total coverage test plan covering unit/cluster/full chip testing with random & corner/boundary test scenarios Focuses on building a well constructed, robust and complete verification environment/test bench Selects aggregate metrics – Functional Coverage, 100% Code Coverage (line, block & toggle coverage) & Traceability Metrics (Avionics DO-254 methodology) based schedule estimates for an executable verification plan

Success Stories: 45nm Wireless SoC Verification: OVM based verification of 45nm wireless, multi-clock System-on-Chip (SoC) for next generation mobiles DO-254 standard SoC Verification for Avionics chip: DO-254 Level A compliant OVM based verification for a 10 million gate count GPS chip HDMI Verification IP: Highly configurable verification IP available in OVM and VMM methodologies, recently adopted by Texas Instruments Wireless Multimedia SoC Verification: SoC Level Verification of different blocks of ARM946E-W88 RISC processor based chip in Vera   Click here to View ASIC-SoC-FPGA Verification Services

Our Differentiators

• Global Customer Exposure (US, Europe, Japan, India) allows us to understand each customer ‘s unique requirements
• Consulting led approach – Developing comprehensive verification environment
  • Give us your Verification Environment and we will provide recommendations on methodologies and mitigating scalability/reusability risks
• Strategically focused on Verification beyond services & solutions
  • Scalable & reusable Verification Environment using layered approach
  • Portfolios of Verification IPs to reduce verification time
  • Unparalleled expertise in reusable VIP Development and Integration
  • HVL expertise in all major languages – SystemVerilog, e, SystemC, Vera
• Ability to rapidly scale team size via training and processes
• Vast proven experience of legacy language migration
  • Verilog/VHDL to SystemVerilog/Vera/C++/e
  • Vera to SystemVerilog/e/C++
  • e to SV/C++/Vera
  • C++ to SV/Vera/e
  • Mixed language VHDL/Verilog into Verilog
• Implements advanced software methodologies for hardware verification
• Unique expertise in modeling system behavior in the verification environment and non-wire bond testing
• Experienced in validating the most complex Verification Environments such as EDA simulators utilizing over 10,000 test cases.
• We can take complete ownership for independent verification tape-out/ Polygon generation
• Low power verification & Negative testing/Error injection verification expertise

Proof Points of our Differentiators

• Developed & licensed number of verification components to 50+ customers
  • eVC solutions for PCI, PCI Express and Gigabit Ethernet under OEM agreement for Verisity/Cadence
  • OVM based IPs PCI, GBE, SPI4.2, I2C, SPI, HDMI, SDIO, AMBA AHB, AXI, MIPI CSI-2
  • VMM compliant HDMI Rev 1.3 MIPI CSI2 for Synopsys end customers
  • PCI/PCI-x , SPI, AMBA AHB, SPI 4 P2, DDR2 SDRAM, USB 2.0, XAUI , I2C , SAS, PS2, SONET , Gigabit Ethernet , PCI express, HDMI VMM-based
• Found 6+ bugs in commercial grade IPs (PCI Express, FM, , AHB, Bluetooth) which were already in market for 2+ years
• Discovered bugs in a silicon proven USB 2.0 Design IP and in USB Verification IP of a leading semiconductor company

Chip / ASIC / SoC Verification Expertise