Intellectual Property

eInfochips’ Intellectual Property cores are fully configurable and programmable for a wide range of performance and power requirements. Our IPs play an instrumental role in reducing the design and verification time for complex SoCs (System-on-Chip) and help you reach your market faster. Our customers enjoy significant advantages in quality and time-to-market for developing complex SoC's for a wide range of end applications ranging from cameras and multi-function printers, to world-class routers and embedded processors.

Synopsys DesignWare® Verification IPs & VMM based IPs

eInfochips was pre-qualified and selected by Synopsys to be a part of the DesignWare Verification IP Alliance program based on its deep experience in verification methodology, VMM and verification IP development. In addition, eInfochips offers a robust IP development methodology, an extensive investment in quality and comprehensive technical support. The Verification IPs included in the Alliance program (HDMI VMM based) were developed using common guidelines to help ensure that a consistent use model is delivered to engineers.

eInfochips is also a member of VMM Catalyst Program that is aimed at accelerating the widespread adoption of the industry-leading VMM verification methodology for SystemVerilog.

OVM Class/Module based IPs:

eInfochips has developed a host of Verification IPs for standard interfaces that are integrated with OVM environment. We have built a 30-engineer OVM trained team to develop, support and integrate into designs, future OVM compliant IP initiatives.

Being a Mentor Graphics Questa Vanguard program member, eInfochips has proven expertise on Questa verification platform which enables us to qualify VIP and provide early support on OVM. As a long-time Cadence Verification Alliance member, eInfochips has expertise in Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) enabling us to provide you all encompassing support on OVM platform.

Besides, being a recognized OVM Partner, einfochips can help facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog (IEEE 1800), SystemC® (IEEE 1666), and e (IEEE 1647) languages leveraging true SystemVerilog interoperability with a standard library and a proven methodology.

Verification IPs

All verification components are configurable, reusable plug-and-play verification solutions that are developed in HVLs (Hardware Verification Languages)- SystemVerilog, Vera, SystemC and e.

Design IPs

The design entry of these IP cores is done in Verilog HDL. These are fully synthesized IP cores, designed to be optimal in terms of power, speed and area and are tested on Xilinx FPGAs. Detailed documentation on design, functional verification and configuration is available. The IP cores can be modified to suit specific design requirements and can also be integrated with customer IP easily.