The MIPI VIP (System Verilog Component :SVC) is compliant to the CSI-2 MIPI Specification for Camera Serial Interface Version 1.00 and DRAFT MIPI Alliance Standard for D-PHY Version 0.85.00.
MIPI Specifications establish standards for hardware and software interfaces between the processors and peripherals typically found in mobile terminal systems. The MIPI VIP is an interface between a digital imaging module such as a host processor and image sensor peripheral such as a camera. It is available as Receiver or Transmitter IP.
eInfochips’ SystemVerilog MIPI verification component is based on a layered object oriented architecture that allows coverage driven system level verification suitable for verification of MIPI transmitter or receiver DUT (Design Under Test).
Features:
The MIPI SystemVerilog VIP generates High Speed, Escape-LPDT, Escape-ULPS and Escape Trigger modes of data traffic with various formats on virtual channels for multiple data lanes. It offers support for error injections and detections for ECC, synchronization, CRC and payload and unrecognized ID detection with an FSM based protocol checker. MIPI Monitor uses SystemVerilog assertion to check for timing violations, if any, at the DPHY interface. Functional coverage mechanism helps determine uncovered configuration variables. MIPI VIP is highly configurable for primary images data formats, number of images (maximum 4), number of lines in the image, number of data-lanes and interleaved image transfers.
Deliverables:
- Completely verified MIPI Verification Component encrypted code
- Documentation - User's Guide, Release Notes
- Sample Test cases
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