AES (Advanced Encryption Standard) IP core provide facility to encrypt or decrypt data according to the needs of environment and user. The AES core interfaces with user interface on one side and memory or any data source on other side. The AES Core implements 128 - bit block size NIST Federal Information Processing Standard 197 AES algorithm.

Main functions of the core are encryption and decryption, which are offered separately to provide optimum flexibility to user for full duplex or half duplex operation.

The encryptor core accepts a 128- bit plaintext input block and generates a corresponding 128-bit ciphertext output using a supplied 128 - bit, 192 - bit, or 256 - bit AESa keys. By using similar AES key as used in encryption; the decryptor core provides the reverse functionality i.e. plaintext generation from the supplied ciphertext.

Features

• Highly optimized for use in Xilinx Spartan2, Spartan2E, Spartan3, VertexE and Vertex2 technologies
• Implements AES (Rijndael) to latest NIST FIPS PUB 197
• Full dynamic supports for all AES key sizes (128, 192 and 256-bits)
• Separate building blocks available for encryption and decryption, can be resource shared to Full Duplex or Half Duplex
• Key expansion can be split out for lower gate count applications