The widely adopted AHB System Bus connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory and interfaces. AHB is a new generation of AMBA bus intended to address the requirements of high-performance synthesizable designs.

eInfochips’ AMBA AHB Verification Component is based on reusable methodology that allows coverage driven verification suitable for verifying Master, Slave and AHB bus with various combinations as the DUT.

Verification Component Overview

AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB VIP is a readymade highly configurable SystemVerilog Verification Component suitable for verification of AMBA AHB master and slave DUT. The AHB SV VIP provides all necessary building blocks to easily test master/slave DUT with the AHB protocol. The Verification Component can be easily configured and integrated with the verification environment.

Features

• Generate Busy, Idle or burst transfers on the AHB bus
  • Gives arbitration at three level of arbitration priority level
  • Generates different kind of response like SPLIT, RETRY, ERROR and OKAY
  • Collects coverage information
  • Checks for AMBA AHB protocol through interface level assertion
  • Support for all kind of burst transfers like SINGLE/INCR/WRAP
  • Support for different size (HSIZE) of transfer
  • Support for multiple bus-widths (32/64 bits)