SPI 3.0 core can be used as a customized bridge solution
for Link Layer to PHY Layer devices packet based interface.
The core will be useful for people who are working on communication
system that is based on point-to-point protocol.
The SPI3 PHY Interface core interfaces between physical link
layer and SPI3 link layer. The Data transfer take place at
speed of 104Mhz on SPI3 Link Interface. The SPI3 interface
core transfer thirty-two bits per clock cycle with in-band
addressing and out band control signals.
Features
- Fully compliant Packet-Over-SONET (POS) PHY level
-3 Link layer Interface.
- Complies with OIF-SPI3-01.0 System packet Interface
Level (SPI-3) Interface.
- Aggregate bandwidth in excess of 2.488 Gbps supporting
OC-48 line rates.
- Four PHY Ports supported.
- High frequency performance on SPI3 side with operating
frequency exceeding 104 MHz.
- High frequency performance on custom proprietary
interface side with operating frequency exceeding
100 MHZ.
- Asynchronous FIFO Interface.
- Direct status mode for four PHY ports.
- Programmable FIFO depth and data segment size.
- Performance monitoring includes parity error and
FIFO over flow.
- Supports performance-monitoring register with separate
Host interface.
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