Overview
SPI-4 is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications.
eInfochips’s SPI4.2 Interface IP is a configurable and an efficient implementation. It is fully compliant to Optical Internetworking forum’s OIF-SPI-4-02.1, System packet interface Level 4 Phase 2 implementation agreement.
Features
- Confirms to OIF SPI 4 Phase 2
- Number of Physical port support scalable up to 256 ports.
- DIP-4 parity generation and checking with programmable error threshold
- Framing error detection and DIP-2 parity generation and checking in status interface
- Fully configurable error reporting and interrupt generation
- 64-bit user logic interface
- Bandwidth optimized design using shared sop-eop control word without filling idle control words
- Supports both interleaved and normal mode of data transfer
- SPI core will detect and generate training
Application
This IP can be used where high speed networking interface is required. This IP can be used, where Queuing, Scheduling, Arbitration and Credit management is done outside the SPI 4.2 IP core. SPI 4.2 IP core gets data for the scheduled port with the address, SOP, EOP, EOP_with_error etc., & SPI core transfers the received data to the port address received. It has only one FIFO rather than per port FIFO.
Deliverables
- Completely verified RTL code for SPI Tx, SPI Rx and configuration interface
- Synthesis Scripts, timing constraints
- Documentation – Design Specs, User Guide
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