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eInfochips’ extensive and innovative Physical Design Services flow is designed to meet the demands of tomorrow's deep sub-micron ASIC designs. Intelligent scripting enables use of EDA tools efficiently in order to achieve a faster time-to-market for your project.
eInfochips specializes in MAGMA design tools for place and route. Our engineers by virtue of their design and verification expertise and experience throughout the physical design flow can ensure that your tape-out is successful.
Physical Design Expertise:
- Low Power Designs
- Clock, Power Gating
- Voltage Scaling
- Multiple Power Domains
- Multi VT Library
- Makefile & Tcl based flow development
- Process expertise 65 – 180nm
- Multiple Clock Domains
- High Speed Interface
- On-chip Analog Blocks
- Latch- based Designs
Processes:

Tools Expertise:
Prototyping & Hierarchy Planning |
First Encounter, BlastPlanPro, JupiterXT |
RTL Synthesis |
Synopsys DC, Cadence RC, Blast Create |
Physical Synthesis |
Synopsys PC, Encounter, Blast Fusion, ICCompiler |
Place, CTS & Route |
Encounter (Nano Route), Blast Fusion, ICCompiler |
Signal Integrity |
PT-SI, Celtic-ndc, BlastNoise, Cool Time |
IR Drop |
Voltage Storm, Blast Rail, Cool Time, Apache |
Static Timing Analysis |
PT-SI, Quartz Time, CTE |
Extraction |
Starrcxt, Fire & Ice, QuartzRC, Columbus |
Layout Verification |
Hercules, Caliber, Assura |
Formal Verification |
Verplex, Formality |
DFT & ATPG |
Syntest flow, Synopsis |
Full Custom Design |
Virtuoso - XL |
Library Development |
Virtuoso - XL |
Flow Development |
Makefile, TCL, Perl |
EM Analysis |
Signal Storm, Blast Noise, CoolTime, Apache |
Power Analysis |
Prime Power, Voltage Storm, Blast Power, Power Theator |
Delivering first time working silicon is essential in today's market. It means not only smooth execution, but also flexibility as market requirements evolve and target markets change. eInfochips experienced engineering team can help you build successive iterations of a design to address a specific customer requirement at a low turnaround time and resource utilization. |
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| Configurable Switch Array |
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Design size: 7 million gates |
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13 Digital Blocks |
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Multi Vt, Flip chip design |
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Process technology: 90n CS |
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9 Metal layers |
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Library: Artisan |
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| 10G Networking Chip |
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Design size: 7 million gates |
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13 Digital Blocks |
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Multi Vt, Flip chip design |
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Process technology: 90nG CS 9M |
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Develop Make and Tcl based flow for RTL2GDSII, Resources management |
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Synthesis, Floorplanning, Place, CTS, Routing, Timing Optimization, Rail Analysis, SI signoff, Layout verification for Digital Blocks. |
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Magma-Mentor tool chain |
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| Digital Video SoC Flip Chip |
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7.9 Million gates, 52 memory, 300 Mhz design, 19 Analog Macros, 14 clocks |
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Flip chip |
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Design Partitioning, Floor planning |
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Placement and CTS |
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Design Integrity Analysis |
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Magma, Synopsys Tool chains |
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| Cell Library Development |
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Cell Library Development |
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Transistor level layout-design of 0.18µ, 0.13µ & 90 nm technology libraries |
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Restructuring for area optimization |
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Elimination of hierarchy |
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Cadence Tool chain |
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