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| Verification & Validation |
eInfochips enables you to rapidly build verification environments for complex, multimillion gate SoC verification, thereby shortening the verification cycle and saving on development cost. Our verification methodology helps build highly layered, scalable, reusable & extensible verification environments for module and SoC level verification, providing maximum functional coverage.
ASIC Verification Services:
- Functional Verification
- Code Coverage Analysis
- Assertion based Verification
- Bus Functional Modeling
- Hardware–Software Co-Verification
- Synthesizable Test Benches
- Protocol Monitors & Checkers
- Formal Verification
- System Simulation
- Full Chip Verification
eInfochips provides end to end verification assurance so that the customers can focus on more critical issues like product conceptualization, architecture, features, performance etc. eInfochips also enables accelerated verification of DUT with independently developed verification IPs. The availability of comprehensive transactions while reducing the simulation runtime also reduces the possibility of a bug staying un-detected.
ASIC Verification Tools Expertise:
Platforms:
Specman, VERA, SystemVerilog,SystemC
Simulators: IUS,NC-Sim, NC-Verilog, Verilog-XL, Questasim, Modelsim, VCS, FinSim
Lint tools: exploreRTL, VeriLint, SureLint, Verix
Code coverage:
CoverMeter, SureCov, HDLScore
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Axis
Palladium
EVE
Mentor Seamless
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Verplex, 0-in
Averant
IFV
Conformal
LEDA
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ASIC Verification Language Expertise:
HDL:
Verilog, VHDL
HVL:
e, VERA,SV, SC
Other:
C. C++
Script:
Perl, Shell script, Tcl/Tk
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HDL:
Verilog, VHDL
Other:
C. C++
Script:
Perl, Shell script, Tcl/Tk
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Our capabilities in Verification include:
- Expertise in HDLs and HVLs
- Full chip verification including IP Cores, automated test benches & regression environment
- Development of regression suites in Specman Elite, C/C++, Vera, Perl and Shell scripts, PLI based verification
- Bus functional models, Protocol monitors and checkers
- Developing automated test benches to create logic and timing verification environment
- Functional and Code coverage analysis
- Experience of working on multi-million gate ASIC / SoC design verification projects
- Extensive portfolio of Verification Components
- Experience in design and verification, and domain knowledge of various technologies like PCI, Ethernet, Fiber Channel, SAS, UWB, USB, I2C, PCI Express, SATA, SPI, HDMI etc.
- Complete verification solutions right from test plan documentation to seeing the silicon tape-out
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| RFID Chip Verification |
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Verification component development & verification environment for modules |
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Comprehensive test plan for various blocks of wireless chip |
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Block level verification and debugging |
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Development of self-diagnostic test cases for efficient debugging |
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Methodology: AVM |
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Platform: SystemVerilog |
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Tools: Questa |
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Complexity: 2 million gate count |
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| Verification of Simulator |
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Development of verification environment & antomation for simulator |
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Comprehensive test plan for various features of verilog LRM 2001 |
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Development of self-diagnostic test cases for efficient debugging |
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Methodology: Coverage driven verification |
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Platform: Verilog, Vera |
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Tools: NC-Sim, VCS |
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Complexity: Approx 40,000 lines of code |
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| HDTV Chip Verification |
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Module/Cluster and full chip verification for DVB-H digital television demodulator |
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ARM946ES Processor and AHB & APB buses |
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Interfaces: I2C, SPI, USB, Ethernet, SDIO peripheral interfaces |
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MPE-FEC decoding |
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MTSP management |
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Methodology: Hardware acceleration |
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Languages: C/C++, Verilog, VHDL, Perl, shell, TCL |
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Tools: LDV5.4, VCS, Linux Enterprise3.0 C/C++ Compiler, Palladium, LEC |
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Complexity: 2.5 million gate |
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| Metro Ethernet Chip Verification |
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Complete block level verification using SystemVerilog VIPs |
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Full Chip verification using SystemVerilog and VMM |
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Methodology: VMM |
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Platform: SystemVerilog |
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Tools: Synopsis VCS |
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Complexity: 11 million gate count |
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