Derivatives can be split into several categories, depending on the market or the evolution of technology at any point in time. Considering the complexity of ASICs and SoCs, most of the chips designed by semiconductor companies are derivatives of their previous generation chips. Although, it gives engineering teams a starting point, it can also add to complexity while integrating IPs, with the potential for increased routing and timing issues.

Leveraging our experience of working on multiple generations of ASIC for leading semiconductor companies and with strong focus on modularity and reusability, eInfochips has developed guidelines, frameworks and reusable verification components to shorten the verification cycle time of these derivative ASICs. At the same time, the physical design team also leverages in-house developed Flow Management System and DFT automation tool to ensure faster tape-out.