The current technology trend focuses on lower nodes of the transistor, which makes accommodating a greater number of transistors in the same size quite easy. Scaling down the technology node has its benefits and flaws. We reduce the supply voltage to protect the cells from an enormous electric field across the gate oxide and the conducting channel. Reduction of supply voltage saves dynamic power dissipation, but it slows down the CMOS transistor. By reducing the voltage, the static power dissipation becomes equal to or more than that of dynamic power dissipation. At lower nodes, leakage power can consume more than 50% of the overall chip power, hence, the high-performance chips have enormous power dissipation, even in the standby mode.

While in the signoff phase, we might look at how fast we can close the design concerning the timing. We generally avoid power optimization while fixing the timing with our standard VT swap and drive strength change techniques. In this paper, we have talked about a different approach to optimize the timing that can improve the leakage power in the lower technology node designs.