The two key parameters of Performance Verification are latency and bandwidth. By latency we mean the time taken by data to reach from one point to another and bandwidth means amount of data transferred in a given time. These two parameters have to be measured and verified against an expected value for all paths of interest and this process is known as performance verification.
With the complexity of SoCs increasing, importance of performance verification grows in verification cycle. So far, there is no standard approach and different approaches are taken based on the individual. In many cases, calculation is done based on reporting using post processing where testcase developer has to print unique and appropriate messages. However this requires development of extra script, overhead in terms of time and effort.
eInfochips has developed a Performance Monitor to standardize the process. It has following features:
PerfMon provides comprehensive PCIe performance visibility with full support for TLP‑level latency and bandwidth analysis, enabling validation of real‑world throughput versus theoretical PCIe limits. Leveraging its protocol‑independent monitoring framework, PerfMon seamlessly adapts to PCIe controllers to analyze PCIe Gen3, Gen4, and Gen5 interfaces across all lane configurations (x1 to x16), helping identify performance bottlenecks and optimize link efficiency.
Supports PCIe Gen3 / Gen4 / Gen5 with lane‑width configurations from x1 to x16 for scalable performance analysis.
TLP‑level latency measurement with sustained and peak bandwidth monitoring to evaluate end‑to‑end performance.
PCIe link utilization, efficiency analysis, and throughput trend visibility to compare achieved bandwidth against expectations.
Congestion, back‑pressure, and traffic burst detection to identify performance degradation and contention points.
Timestamped PCIe transaction traces with error, retry, timeout, and AXI cross‑protocol correlation for system‑level performance optimization.
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